1. Field of the Invention
The present invention relates to a clock distribution method for setting an optimal skew of a logic circuit, which obtains an optimal skew between registers on an LSI clock tree circuitry, a clock tree generating method to structure a clock tree when a useful skew is used, a clock delay setting method to minimize noise generated by a circuit, and a circuitry process method for a logic circuit using a useful skew.
2. Description of the Related Art
Conventionally, in digital logic integrated circuits, sequential circuits, typically registers and flip-flop circuits, are used, and the entire of the circuit operates in synchronization with a plurality of clock signals each of which are at a different phase and cycle.
It is common that the propagation delay time (hereinafter referred to as “delay”) of clock signals to be supplied to the flip-flop circuits differ for each flip-flop circuit, and a phase difference associated therewith is called a clock skew (hereinafter referred to as “a skew”). One problem, which arises quite often in designing digital logic integrated circuits, is that this skew becomes so large that the synchronization operation of circuits cannot be performed at a desired clock frequency. For this reason, an on-chip clock skew reduction method is proposed, and a skew value zero is provided between each register included in the sequential circuit and other registers which have the relationship of the connection of a signal that has passed through a combinational circuit therebetween.
However, in place of the so-called zero skew, in which skew value zero is provided between each register included in the sequential circuit and other registers which have the relationship of connection of a signal that has passed through a combinational circuit therebetween, in recent years there is a method using a useful skew that provides a skew value Δ therebetween. This makes it possible to avoid simultaneous switching of flip-flop circuits to reduce a peak value and to reduce the generation of noise. Also, this makes it possible to stabilize a circuit voltage. Moreover, in the case of zero skew, if even one flip-flop circuit of the logic circuit does not satisfy a predetermined requirement, the entirety of circuit does not work well. However, the use of useful skew makes it possible to operate a flip-flop circuit which does not require the predetermined requirement in the case of zero skew properly, and to avoid a problem in which the entirety of circuit does not work well.
Regarding the circuitry process of the aforementioned logic circuit, as illustrated in FIG. 1, after performing a data path section delay calculation process S11, a clock delay assignment process S12 and a clock circuitry process S13 in a cell positioning process S10, an outline circuitry process S20 for general signal circuitry is carried out Thereafter, a specific circuitry process S30 for general signal circuitry is performed, so that the circuitry is ended.
Alternatively, as illustrated in FIG. 2, after performing the data path section delay calculation process S11 and the clock delay assignment process S12 in the cell positioning process S10, the outline circuitry process S20 for general signal circuitry is carried out. Thereafter, in the specific circuitry process S30 for general signal circuitry, a clock circuitry process S31 is performed to end the circuitry.
A “Clock distributing method” using the above-explained useful skew, which is disclosed in Japanese Patent Laid-Open No. 10-326303, can be explained as follows:
Specifically, for forming a clock tree, a delay analysis is carried out to obtain an allowance with respect to constraint time for both input and output sides for each flip-flop circuit to insert delay to a clock. Then, a suitable flip-flop circuit is selected from among the flip-flop circuits that meet this constraint at both sides even if delay is inputted to the clock, and delay is inputted to the clock to make a difference with respect to a change in the other clocks so as to avoid a concentration of change in the clock.
This method has the problem as follows.
Specifically, consideration is given to only the point set forth below:
Namely, a subgroup of flip-flops is taken from the flip-flop circuits in the circuit, and delay is added to clock signals of these circuits uniformly or reduced so as to decrease a peak current.
However, it is a precondition that no violation of timing constraint exists in the logic circuit. The above method does not consider the reduction of violation by adding and subtracting the delay of clock signals when the violation of timing constraint exists before this method is applied. Accordingly, this method does not fully bring out the merit of using the useful skew.
Clockwise processing by Ultima described in “Using clock skew for optimaltiming” in the article of “Integrated System Design” April, 1999(http://isdmag.com) is also one of conventional methods using the useful skew. This method can be explained as follows:
Specifically, a permissible range or a skew boundary of a skew value between registers is gained based on a maximum delay time of the combinational circuit between the registers, a minimum delay time thereof and a clock cycle. Next, the skew value between the respective registers is set to a value, which is as close as possible to the center of the skew boundary, such that no contradiction occurs between all registers. In this article at least, there is no description of a specific method for reducing the clock cycle to accelerate the circuit operation. In addition, there is a description about reduction in the peak current value because of the fact that zero skew is not applied. However, there is no description about an algorithm such as a point that the skew value is aggressively set to a value away from the center of the skew boundary, thereby reducing the peak current value positively.
Moreover, in addition to the foregoing, in the conventional method, the presence of combinational circuits among all registers and the provision of the signal delay time information are preconditions. However, in the large-scaled circuit, it is not uncommon for the number of registers to exceed a few thousands, so that the number of combinational circuits among the registers becomes considerably large. Accordingly, the presence of combinational circuits among all registers and the signal delay time information enormously increases, causing a problem of increasing necessary memory amounts and processing time.
Still moreover, in addition to the foregoing, the conventional method is equally compliant with setup time constraints and hold time constraints of the circuit For this reason, in the circuit when both constraints are severe, both the violation of setup constraint (constraint of an upper limit to signal delay time between two points) and that of hold time constraint (constraint of a lower limit to signal delay time between two points) are left at the same amount even if the useful skew is used.
The violation of setup time constraint is solved by the adjustment of the clock frequency, and that of hold time constraint is solved by the adjustment of the clock skew. Namely, since two different solution methods had to be provided, there was difficulty in correcting the circuit afterward in some cases.
In structuring the clock tree when the useful skew is used as mentioned above, there have been cases in which the skews are not reduced sufficiently when a bias is found in the distribution of the presence of F/F on the chip, for example, when an extremely small number of F/Fs is found in the vicinity of a root driver while a large number of F/Fs is found at a distance, in an H tree-type clock layout, which is a conventional tree generating method. At such times, the layout that satisfies the delay constraint is not achieved in some cases since an alternative path was generated as compared with a case in which the root driver and each F/F are connected at the shorted path of point to point, in terms of the tree structure. Also, there has been a case in which a useless buffer is inserted or an alternative path is generated in order to reduce the skews.
Further, in the conventional circuitry process of the aforementioned logic circuit, after cell positioning process is performed and before circuitry is performed, (1) data path section delay calculation process and (2) clock delay assignment process are performed. For this reason, no consideration is given to the clock delay due to circuitry, and there has been concern that accuracy is poor and the clock can not be delayed according to the design when delay in the clock is slightly adjusted by use of the useful skew.